1. Field
Exemplary embodiments of the present invention relate to a semiconductor designing technology, and more particularly, to a low pre-decoder circuit of a semiconductor memory device.
2. Description of the Related Art
Semiconductor memory devices including Dynamic Random Access Memory (DRAM) devices are using a row/column addressing scheme. First, a row address is inputted from the outside to select a row, which is a word line, and then a column address is inputted from the outside to select a column of the selected row, which is a bit line.
Conventionally, since there are many rows and columns, a method of decoding an address of multiple bits is being used. To taken an example of row addressing, a scheme where a pre-decoder is disposed in front of a main decoder and a word line driver to minimize the circuit area needed for a decoding circuit.
Meanwhile, word lines are generally formed of polysilicon to overcome technical limitation. However, since polysilicon has a high electrical resistance, a hierarchical structure of main word lines that are formed of metal and sub-word lines that are formed of polysilicon is being used. Generally, four sub-word lines are assigned to one main word line. The word line forming one page has a great loading in terms of a driving circuit, the sub-word lines are disposed over a half of one page. In other words, as illustrated in FIG. 1, which illustrates a pre-decoding scheme for selecting a half page by using the Most Significant Bit (MSB) of a row address, although word lines WL_L<0> and WL_R<0> form one page, they are disposed on a left block BLOCK_L and a right block BLOCK_R of each bank to form a half page, individually. Herein, row address-related signals LAX01, LAX23, . . . , LAXD are the output signals of a row pre-decoder. Among the row address-related signals LAX01, LAX23, . . . , LAXD, the row address-related signal LAXD selects the left block BLOCK_L and the right block BLOCK_R. The row address-related signal LAXD is a signal obtained by pre-decoding the most significant bit among the multiple bits that constitute the row address. For example, when the row address has 14 bits, the <0>th word line is selected based on an address A<0:12>, and the word line WL_L<0> of the left block BLOCK_L or the word line WL_R<0> of the right block BLOCK_R is selected based on the most significant bit, which is the address A<13>.
When there is an external interface that processes data in parallel, a plurality of data input/output pins are used. Generally, there are such data width options as X4 mode, X8 mode, and X16 mode. In case of the X4 mode, data are inputted/outputted through four data input/output pins among the data input/output pins. In case of the X8 mode, data are inputted/outputted through eight data input/output pins among the data input/output pins. The semiconductor memory device is designed to support all data width options, and the data width options are set through wire bonding or fuse option.
Meanwhile, when only a portion of the external data input/output pins is used, such as the X4 mode and the X8 mode, the left block BLOCK_L of FIG. 1 is used. However, as illustrated in X16 mode, when the entire external data input/output pins are to be used, both of the left block BLOCK_L and the right block BLOCK_R have to be selected simultaneously. Moreover, it does not have to distinguish the left block BLOCK_L and the right block BLOCK_R from each other for access when a row address is generated internally in a refresh operation duration, too.
Therefore, the unit pre-decoding circuit that corresponds to the MSB in the pre-decoder that receives the row address additionally includes a control circuit to select the whole page in the X16 mode or the refresh mode, differently from the unit pre-decoding circuit that corresponds to the other lower bits.
FIG. 2 is a circuit diagram illustrating a conventional row pre-decoder. The drawing shows a unit pre-decoding circuit that corresponds to the most significant bit of the pre-decoder.
Referring to FIG. 2, the conventional pre-decoding circuit includes an input unit 200, a control signal generation unit 240, a first mode control unit 210, a second mode control unit 215, a first driving unit 220, a second driving unit 225, a first latch unit 230, and a second latch unit 235. The input unit 200 receives a row address XA<13> in response to a bank active pulse BAP and a row address enable pulse XAEP. The control signal generation unit 240 outputs a mode control signal MODECTRL in response to a refresh signal REF and an X16 mode signal SIG_X16. The first mode control unit 210 transfers a first output signal of the input unit 200 corresponding to the row address XA<13> in response to the mode control signal MODECTRL. The second mode control unit 215 transfers a second output signal of the input unit 200 corresponding to an inverse signal of the row address XA<13> in response to the mode control signal MODECTRL. The first driving unit 220 pull-up/pull-down drives an output terminal that corresponds to a first pre-decoding signal LAXD<0> in response to a row active signal R3ACB and the output signal of the first mode control unit 210. The second driving unit 225 pull-up/pull-down drives an output terminal that corresponds to a second pre-decoding signal LAXD<1> in response to the row active signal R3ACB and the output signal of the second mode control unit 215. The first latch unit 230 latches the output signal of the first driving unit 220, and the second latch unit 235 latches the output signal of the second driving unit 225.
Herein, the input unit 200 includes a NAND gate ND1, an inverter IN0, an inverter IN1, an inverter IN2, a NAND gate ND2, and a NAND gate ND3. The NAND gate ND1 receives the row address XA<13> and the bank active pulse BAP. The inverter IN0 receives the output signal of the NAND gate ND1. The inverter IN1 receives the output signal of the inverter IN0. The inverter IN2 forms an inverse latch together with the inverter IN1. The NAND gate ND2 receives the output signal of the inverter IN1 and the row address enable pulse XAEP. The NAND gate ND3 receives the output signal of the inverter IN0 and the row address enable pulse XAEP.
The control signal generation unit 240 includes a NOR gate NR1 that receives the refresh signal REF and the X16 mode signal SIG_X16 and receives the mode control signal MODECTRL.
The first mode control unit 210 includes a NAND gate ND4 and an inverter IN3. The NAND gate ND4 receives the mode control signal MODECTRL and a first output signal of the input unit 200. The inverter IN3 receives the output signal of the NAND gate ND4.
The second mode control unit 215 includes a NAND gate ND5 and an inverter IN4. The NAND gate ND5 receives the mode control signal MODECTRL and a second output signal of the input unit 200. The inverter IN4 receives the output signal of the NAND gate ND5.
The first driving unit 220 includes a PMOS transistor MP0, a PMOS transistor MP1, and an NMOS transistor MN0. The PMOS transistor MP0 includes a source coupled with a power source voltage VDD terminal and a gate for receiving the output signal of the first mode control unit 210. The PMOS transistor MP1 includes a source coupled with a drain of the PMOS transistor MP0, a drain coupled with an output terminal, and a gate for receiving the row active signal R3ACB. The NMOS transistor MN0 includes a source coupled with a ground voltage VSS terminal, a drain coupled with an output terminal, and a gate for receiving the row active signal R3ACB.
The second driving unit 225 includes a PMOS transistor MP2, a PMOS transistor MP3, and an NMOS transistor MN1. The PMOS transistor MP2 includes a source coupled with a power source voltage VDD terminal and a gate for receiving the output signal of the second mode control unit 215. The PMOS transistor MP3 includes a source coupled with a drain of the PMOS transistor MP2, a drain coupled with an output terminal, and a gate for receiving the row active signal R3ACB. The NMOS transistor MN1 includes a source coupled with a ground voltage VSS terminal, a drain coupled with an output terminal, and a gate for receiving the row active signal R3ACB.
The first latch unit 230 includes an inverter IN5, an inverter IN6, and an inverter IN7. The inverter IN5 receives the output signal of the first driving unit 220. The inverter IN6 forms an inverse latch together with the inverter IN5. The inverter IN7 receives the output signal of the inverter IN5 and outputs the first pre-decoding signal LAXD<0>.
The second latch unit 235 includes an inverter IN8, an inverter IN9, and an inverter IN10. The inverter IN8 receives the output signal of the second driving unit 225. The inverter IN9 forms an inverse latch together with the inverter IN8. The inverter IN10 receives the output signal of the inverter IN8 and outputs the second pre-decoding signal LAXD<1>.
FIGS. 3A and 3B are timing diagrams of the row pre-decoding circuit illustrated in FIG. 2. The operation of the row pre-decoding circuit illustrated in FIG. 2 is described with reference to the drawings.
First of all, FIG. 3A illustrates the semiconductor memory device performing a normal-mode operation in the X4 mode or the X8 mode.
Referring to FIG. 3A, when an active command is applied, the bank active pulse BAP is enabled to a logic high level, and then the row address enable pulse XAEP is enabled to a logic high level. Therefore, the first output signal of the input unit 200 is outputted in the same logic level as the row address XA<13>, and the second output signal of the input unit 200 is outputted in the opposite logic level as the row address XA<13>.
The refresh signal REF is a signal that is enabled to a logic high level in a refresh duration and it is disabled to a logic low level in a normal mode. Also, since the mode is not the X16 mode, the X16 mode signal SIG_X16 is disabled to a logic low level as well. Therefore, the mode control signal MODECTRL is of a logic high level, and the first mode control unit 210 and the second mode control unit 215 transfer the first and second output signals of the input unit 200 as they are.
The row active signal R3ACB receives the active command to be enabled to a logic low level, and it receives a precharge command to be disabled to a logic high level. Herein, since the row active signal R3ACB is enabled to a logic low level, the PMOS transistor MP1 of the first driving unit 220 and the PMOS transistor MP3 of the second driving unit 225 are turned on. Therefore, the PMOS transistor MP0 of the first driving unit 220 and the PMOS transistor MP2 of the second driving unit 225 are selectively turned on according to the row address XA<13>.
After all, the first pre-decoding signal LAXD<0> and the second pre-decoding signal LAXD<1> that are outputted from the first latch unit 230 and the second latch unit 235 selectively transition to a logic high level according to the logic level of the row address XA<13>, and another signal maintains its logic level in the logic low level. This is because the first latch unit 230 and the second latch unit 235 are initialized to a logic low level based on the row active signal R3ACB that is disabled to a logic high level in the precharge operation before the reception of the active command.
Meanwhile, when the precharge command is applied, the row active signal R3ACB is disabled to a logic low level. Therefore, the first pre-decoding signal LAXD<0> and the second pre-decoding signal LAXD<1> that are outputted from the first latch unit 230 and the second latch unit 235 are all initialized to a logic low level regardless of the row address XA<13>.
The drawings show a case where the row address XA<13> is in a logic low level, and during the active operation, the first pre-decoding signal LAXD<0> is in a logic high level and the second pre-decoding signal LAXD<1> is in a logic low level. However, when the row address XA<13> is in a logic high level, the polarity of the signals becomes the opposite.
As described above, when the semiconductor memory device is set in the X4 mode or the X8 mode and performs a normal-mode operation, any one between the first pre-decoding signal LAXD<0> and the second pre-decoding signal LAXD<1> transitions to a logic high level. As described earlier, the MSB, e.g., address A<13>, of the row address selects the half page to be enabled. Therefore, a word line of the left block BLOCK_L or a word line of the right block BLOCK_R shown in FIG. 1 is selectively enabled according to the logic level of the first pre-decoding signal LAXD<0> and the second pre-decoding signal LAXD<1>.
Subsequently, FIG. 3B illustrates an operation in a refresh mode when the semiconductor memory device is set in the X16 mode, or when the semiconductor memory device is set in the X4 mode or the X8 mode.
Referring to FIG. 3B, when the active command is applied, the bank active pulse BAP is enabled to a logic high level, and then the row address enable pulse XAEP is enabled to a logic high level. Therefore, the first output signal of the input unit 200 is outputted in the same logic level as that of the row address XA<13>, and the second output signal of the input unit 200 is outputted in the opposite logic level to the logic level of the row address XA<13>.
When the semiconductor memory device is set in the X16 mode, the X16 mode signal SIG_X16 always maintains its logic state to be enabled in a logic high level. Also, when the semiconductor memory device is set in the X4 mode or the X8 mode, the X16 mode signal SIG_X16 is disabled to a logic low level, but the refresh signal REF is enabled to a logic high level during a refresh operation. Therefore, when the semiconductor memory device is set in the X16 mode or when the semiconductor memory device is set in the X4 mode or the X8 mode and the mode is a refresh mode, the mode control signal MODECTRL is in a logic low level while the first mode control unit 210 and the second mode control unit 215 output a signal of a logic low level regardless of the first and second output signals of the input unit 200.
Since the row active signal R3ACB is enabled to a logic low level during an active operation, the PMOS transistor MP1 of the first driving unit 220 and the PMOS transistor MP3 of the second driving unit 225 are turned on. Herein, since the output signals of the first mode control unit 210 and the second mode control unit 215 are all of a logic low level regardless of the row address XA<13>, the PMOS transistor MP0 of the first driving unit 220 and the PMOS transistor MP2 of the second driving unit 225 are all turned on.
After all, since the first pre-decoding signal LAXD<0> and the second pre-decoding signal LAXD<1> that are outputted from the first latch unit 230 and the second latch unit 235 all transition to a logic high level.
Meanwhile, when a precharge command is applied, the row active signal R3ACB is disabled to a logic low level. Therefore, the first pre-decoding signal LAXD<0> and the second pre-decoding signal LAXD<1> that are outputted from the first latch unit 230 and the second latch unit 235 are all initialized to a logic low level, regardless of the row address XA<13>.
As described above, when the semiconductor memory device is set in the X16 mode, both of the first pre-decoding signal LAXD<0> and the second pre-decoding signal LAXD<1> toggle to a logic high level whenever a bank is activated, regardless of the operation mode; and an operation that the first pre-decoding signal LAXD<0> and the second pre-decoding signal LAXD<1> toggle to a logic low level is performed repeatedly whenever the bank is precharged. Also, although the semiconductor memory device is set in the X4 mode or the X8 mode, if a refresh operation is continuously performed, both of the first pre-decoding signal LAXD<0> and the second pre-decoding signal LAXD<1> toggle to a logic high level whenever a bank is activated; and whenever the bank is precharged, the operation that the first pre-decoding signal LAXD<0> and the second pre-decoding signal LAXD<1> toggle to a logic low level is performed repeatedly. Herein, when the semiconductor memory device gets out of the refresh mode, both of the first pre-decoding signal LAXD<0> and the second pre-decoding signal LAXD<1> are all initialized to a logic low level, and then the semiconductor memory device performs the operation of FIG. 3A afterwards.
When the semiconductor memory device is set in the X16 mode, the entire page is selected; or although the semiconductor memory device is set in the X4 mode or X8 mode, if the mode is a refresh mode, the entire page is selected basically. Therefore, although it does not have to select a half page, initializing the first pre-decoding signal LAXD<0> and the second pre-decoding signal LAXD<1> to a logic low level whenever a bank is precharged after the bank is activated requires unnecessary toggling, which means unnecessary current consumption.